Flip-chip semiconductor package is formed by mounting and electrically connecting an active surface of at least one chip to a surface of a substrate via a plurality of solder bumps through the use of a flip-chip technique, and implanting a plurality of solder balls serving as input/output (I/O) connections on another surface of the substrate to allow the chip to be electrically connected to an external device via the solder balls. The flip-chip semiconductor package is advantageous of having a reduced size to make the chip and the substrate similar in scale and avoiding the use of bonding wires to thereby reduce resistance and improve electrical performance thereof, such that the flip-chip semiconductor package is widely used.
FIGS. 1A and 1B show a conventional flip-chip semiconductor package, which requires filling of an underfill material 12 (such as a thermosetting material) between a chip 10 and a substrate 11 on which the chip 10 is mounted so as to allow the underfill material 12 to encapsulate solder bumps 13 that electrically connect the chip 10 to the substrate 11, such that the solder bumps 13 are enhanced in strength, secured in place and prevented from deformation as well as can support the weight of the chip 10. The underfilling process has been disclosed in prior technologies such as U.S. Pat. Nos. 5,672,548 and 6,008,534.
Due to surface tension of the underfill material 12 filled between the chip 10 and the substrate 11, the four corners of the chip 10 are covered by a relatively smaller or the smallest amount of the underfill material 12 (as indicated by S in FIG. 1A) as compared to other areas of the chip 10. Further, due to a great mismatch in coefficient of thermal expansion (CTE) between a material of the chip 10 and a material of the substrate 11, thermal stress and thermal deformation are proportional to distance L in a thermal cycle during fabrication of the semiconductor package, that is, δ (quantity of deformation)=α (CTE)×L (distance from a position where δ is zero)×Δt (quantity of temperature change). In other words, a corner position of the chip 10 would experience the maximum thermal stress and thermal deformation as the corner position has the furthest distance from a central position of the chip 10 where the quantity of deformation δ is zero. However, the underfill material 12 cannot provide sufficient protection at the corner position of the chip 10 as not being covered by a sufficient amount of the underfill material 12, thereby making the corner position of the chip 10 delaminate from the underfill material 12 (as indicated by S′ in FIG. 1A) and adversely affecting the quality of underfilling. The electrical performance of the solder bumps may even be deteriorated if the delamination spreads.
Accordingly, as disclosed in U.S. Pat. Nos. 6,225,704 and 6,372,544, a fillet 24 is provided around the underfill material 22 to encapsulate the underfill material 22 and improve the protection effect as shown in FIG. 2.
However, to have the arrangement of FIG. 2, an additional process of applying the fillet 24 around the underfill material 22 after completing the underfilling process is required, which undesirably increases the time, steps and cost in fabrication and easily causes flashes of the fillet 24.
FIGS. 3A to 3C show another type of underfiling technology as disclosed in U.S. Pat. No. 5,892,289. By this type of underfiling technology, a sealing resin 32 is applied at the four corners of a chip mounting area on a substrate 31, and then a chip 30 is mounted and electrically connected to the chip mounting area of the substrate 31, allowing the sealing resin 32 applied on the corners of the chip mounting area to slowly flow towards the center of the chip mounting area and fill a gap between the chip 30 and the substrate 31 by capillary action. As a result, the four corners of the chip 30 can be covered by more resin and thus provided with better protection.
However, during practical implementation, it is difficult to control the amount of resin formed on the corners of the chip mounting area and the fluidity of resin through the capillary action, which may cause an insufficient amount of resin filled between the chip and the substrate such that bonding quality of the chip and the substrate is degraded, or cause an excessive amount of resin filled between the chip and the substrate such that bond pads on the substrate could be contaminated by the resin, thereby adversely affecting the reliability of the fabricated packaged product.
Therefore, the problem to be solved here is to provide a flip-chip semiconductor device for preventing delamination at corners of a chip incorporated in the semiconductor device.